1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of forming amorphous silicon layer on one side of the gate structure and contact plug on another side of the gate structure.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the FinFET can be controlled by adjusting the work function of the gate.
Typically, contact areas for contact plugs decrease substantially after the fabrication of semiconductor device enters 10 nm node and results in increase of resistance. Moreover, the fabrication of contact plugs also requires more masks to be used. The increase of masks further induces an increase in resistance when even a little shift is found in active region and degrades the operation of the device. Hence, how to resolve this issue has become an important task in this field.